(a) Field of the Invention
The present invention relates to a wiring board for use in mounting an electronic component such as a semiconductor device. More particularly, the present invention relates to a wiring board (hereinafter referred to also as a “semiconductor package”) adapted for mounting an electronic component using a thermosetting material, the wiring board having a structure in which a plurality of wiring layers are stacked one on top of another with an insulating layer interposed therebetween and are interconnected through via holes formed in the insulating layer, and to an electronic component device including the wiring board with an electronic component mounted thereon.
(b) Description of the Related Art
Heretofore, build-up process has been widely used as a technology for manufacturing a wiring board of multilayer structure. With the use of the build-up process, a variety of multilayer wiring boards can be fabricated by varying the combination of a material (typically, a resin) for an interlayer dielectric and a via hole formation process. A typical manufacturing process for the multilayer wiring board using the build-up process is to repeat, in turn, the formation of an insulating layer, the formation of a via hole in the insulating layer, and the formation of a wiring pattern on the insulating layer and also in the via hole, on both surfaces or either one surface of a core substrate serving as a support base member. In such a structure, wiring layers and insulating layers can be thinly formed since the build-up process is used for their stacking, while the core substrate requires an appropriate thickness for affording the wiring board rigidity. This leads to a limitation to making the entire semiconductor package thinner.
Thus, a structure without a core substrate (support base member) has recently been adopted to make a wiring board (semiconductor package) to still thinner. The wiring board of such a structure is also called a “coreless substrate” in the meaning that it has no “core” portion. Although description is given later with respect to a method of manufacturing such a coreless substrate, the basic process thereof includes: preparing a temporary substrate as a support; forming, in sequence, a desired number of build-up layers (namely, insulating layers including via holes, and wiring patterns including the insides of the via holes) on the temporary substrate; and removing the temporary substrate (support).
An example of the technology related to the above conventional art is disclosed in Japanese unexamined Patent Publication (Kokai) 2000-323613. The technology disclosed in this publication provides a multilayer wiring board for a semiconductor device, and in the multilayer wiring board, a mounting surface for mounting the semiconductor device is formed as flat and thin as possible.
As mentioned above, the conventional coreless substrate (semiconductor package) has an advantage of allowing a reduction in thickness thereof since it does not need a core substrate. On the other hand, the conventional coreless substrate has a disadvantage of being prone to “warpage” since the absence of the core substrate affords the overall package low rigidity.
This problem develops more markedly when a chip is mounted on the substrate. FIGS. 8A and 8B show an example of the problem.
First, as shown in FIG. 8A, bumps (electrode terminals) 61 are formed on a chip 60 to be mounted on a coreless substrate 50. Thereafter, the electrode terminals 61 of the chip 60 are electrically connected to pad portions 51 exposed from one surface (in the illustrated example, the upper side surface) of the coreless substrate 50 (namely, flip chip bonding). Then, as shown in FIG. 8B, an underfill resin 70 is filled into a gap between the substrate 50 and the chip 60 to thereby insulate and shield the contact portion therebetween (namely, the pad portions 51 and the electrode terminals 61) from the outside. At that time, the underfill resin 70 is subjected to baking (namely, heat treatment) in order to undergo heat curing; however, the coefficient of thermal expansion of the underfill resin 70 is different from that of the substrate 50, and thus, as shown in FIG. 8B, the underfill resin 70 shrinks, so that the periphery of the substrate 50 is warped upward (namely, toward the chip 60).
Thus in the structure of the conventional coreless substrate (semiconductor package), on the occasion of chip mounting, the “warpage” occurs resulting from the low rigidity of the overall package and can possibly cause chip delamination depending on the degree of warpage, which in turn leads to a problem of making it impossible to implement the chip mounting with a high degree of reliability.
Additionally, the timing of the warpage to occur in the substrate is not limited to only the time of chip mounting, and the warpage may possibly occur even at stages before chip mounting. For example, in the case where a careless substrate is delivered to customer sites and then a chip is mounted thereon on the customer's premises, the warpage can possibly occur in the substrate, depending on how the substrate is handled during the processes from the delivery to the mounting, because the coreless substrate is intrinsically low in rigidity and flexible.
Moreover, this problem is not always unique to the coreless substrate and may possibly arise likewise in a build-up multilayer wiring board having the core substrate. Specifically, the coefficient of thermal expansion of a material constituting the wiring layer, such as copper (Cu), is significantly different from that of a material constituting the insulating layer, such as an epoxy resin. Thus, the application of the approach of building up the wiring and insulating layers alternatingly with one on top of another to one surface of the core substrate at given intervals of time (namely, the build-up process) can possibly induce thermal stress at the interface between the wiring layer and the insulating layer in the thickness direction of the layers according to the difference in the coefficient of thermal expansion during the process of building up. As a result, the warpage may occur in the substrate.